阅读 以下程序,绘制模块图电路,并简述其功能 LIBRARY IEEE; USE IEEE.STD_LOGIC_11.ALL ; ENTITY ENCODER IS PORT (A , B , C , D , E , F , G , H : IN STD_LOGIC : Y_0 , Y_1 , Y_2 : OUT STD_LOGIC) ; END ENCODER ; ARCHITECTURE ART1 OF ENCODER IS SIGNAL OUTS : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN OUTS (2 DOWNTO 0)<= "111" WHEN H=‘1’ ELSE "110" WHEN G=‘1’ ELSE "101" WHEN F=‘1’ ELSE "100" WHEN E=‘1’ ELSE "011" WHEN D=‘1’ ELSE "010" WHEN C=‘1’ ELSE "001" WHEN B=‘1’ ELSE "000" WHEN A=‘1’ ELSE "XXX" ; Y_0<=OUTS(0) ; Y_1<=OUTS(1) ; Y_2<=OUTS(2) ; END ART1 ;